As is well known, a solid state drive (SSD) is a data storage device that uses a non-volatile memory to store data. After data are written to the flash memory, if no electric power is supplied to the flash memory, the data are still retained in the solid state drive.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state drive. As shown in FIG. 1, the solid state drive 10 comprises a controlling circuit 110, a buffering element 130 and a non-volatile memory 120. The controlling circuit 110 is in communication with a host 12 through an external bus 20. Consequently, commands and data can be exchanged between the controlling circuit 110 and the host 12. Generally, the external bus 20 is a USB bus, an SATA bus, a PCIe bus, or the like. For example, the buffering element 130 is a volatile memory such as a dynamic random access memory (DRAM).
In the solid state drive 10, the controlling circuit 110 is connected with the buffering element 130 and connected with the non-volatile memory 120 through an internal bus 115. Generally, the buffering element 130 comprises a data buffer for temporarily storing the write data from the host 12 or temporarily storing the read data to be outputted to the host 12.
Generally, the non-volatile memory 120 is composed of one or more chips. In each chip, the storage space is divided into plural blocks. Each block comprises plural pages. Due to the inherent properties of the non-volatile memory, at least one page is written at a time during the writing operation, and the erasing operation is performed in a block-wise fashion. For example, each block comprises 256 pages. Each page is typically 4K bytes or 2K bytes in size.
For increasing the storing capability of the solid state drive 10, the non-volatile memory 120 is composed of plural chips. As the number of chips in the non-volatile memory 120 increases, the storing capability of the solid state drive 10 increases.
For allowing the controlling circuit 110 to access the chips of the non-volatile memory 120 more efficiently and comply with the accessing specification of the non-volatile memory 120, the solid state drive 10 accesses the non-volatile memory 120 according to a superblock configuration. In the solid state drive 10, the corresponding blocks of these chips are defined as a superblock. The plural chips can be controlled and accessed simultaneously through the superblock, and thus the efficiency of accessing the non-volatile memory 120 is enhanced. In other words, the non-volatile memory 120 comprises plural superblocks, and each superblock comprises plural superpages.
FIG. 2 schematically illustrates the architecture of the non-volatile memory of the conventional solid state drive. The internal bus 115 between the non-volatile memory 120 and the controlling circuit 110 comprises plural control signal lines, for example, 8 channels ch0˜ch7 and 4 chip enable signal lines CE0˜CE3.
As shown in FIG. 2, the non-volatile memory 120 comprises 32 chips c00˜c73. Please refer to the arrangement of the chips in a first direction (e.g., the vertical direction). The channel ch0 is connected with the chips c00˜c03. The channel ch1 is connected with the chips c10˜c13. The channel ch2 is connected with the chips c20˜c23. The channel ch3 is connected with the chips c30˜c33. The channel ch4 is connected with the chips c40˜c43. The channel ch5 is connected with the chips c50˜c53. The channel ch6 is connected with the chips c60˜c63. The channel ch7 is connected with the chips c70˜c73.
Please refer to the arrangement of the chips in a second direction (e.g., the horizontal direction). The chip enable signal line CE0 is connected with the chips c00˜c70. The chip enable signal line CE1 is connected with the chips c01˜c71. The chip enable signal line CE2 is connected with the chips c02˜c72. The chip enable signal line CE3 is connected with the chips c03˜c73.
The control signal lines are connected with all of the chips c00˜c73. These control signals lines are used for transferring control signals. The control signals contain a command latch enable signal CLE, an address latch enable signal ALE, a read enable signal RE, a write enable signal WE, a write protect signal WP, a ready/busy signal (R/B), and so on.
During the process of accessing the non-volatile memory 120, the controlling circuit 110 selects an opened superblock according to a block number. Moreover, the physical blocks of the chips c00˜c73 corresponding to the block number are opened physical blocks. In other words, the opened superblock is equivalent to the set of the opened physical blocks in the chips c00˜c73. Moreover, the controlling circuit 110 controls the channels ch0˜ch7 and the chip enable signal lines CE0˜CE3 to determine the opened physical blocks of the specified chip. That is, the set of the corresponding physical blocks of these chips are defined as a superblock.
For example, in case that each chip of FIG. 2 comprises 1024 physical blocks and each physical block comprises 256 physical pages, the non-volatile memory 120 comprises 1024 superblocks and each superblock comprises 256 superpages.
FIG. 3 schematically illustrates a superblock mapping structure of the non-volatile memory. Generally, the n-th superblock sbn of the non-volatile memory 120 is mapped to the n-th physical blocks b00n˜b73n of the chips c00˜c73, wherein n is an integer in the range between 1 and 1024. As shown in FIG. 3, the n-th physical block of the chip c00 is indicated as b00n, the n-th physical block of the chip c10 is indicated as b10n, and the rest may be deduced by analogy.
If n=1, the set of the 32 first physical blocks of the 32 chips c00˜c73 are collaboratively defined as a first superblock. If n=2, the set of the 32 second physical blocks of the 32 chips c00˜c73 are collaboratively defined as a second superblock. The other superblocks have the similar mapping structures.
Moreover, as shown in FIG. 3, the first physical page in the n-th physical block of the chip c00 is indicated as p001, the first physical page in the n-th physical block of the chip c10 is indicated as p101, and the rest may be deduced by analogy.
The set of the first physical pages in the 32 n-th physical blocks of the 32 chips c00˜c73 are collaboratively defined as a first superpage sp1. That is, the first superpage sp1 in the n-th superblock sbn is the set of the 32 first physical pages p001˜p731. The other superpages in the n-th superblock sbn have the similar mapping structures.
A process of writing a 32-page data into the first superpage sp1 of the n-th superblock sbn will be described as follows. Firstly, the 32-page data is divided into four 8-page data. Then, the chip enable signal line CE0 is activated, and the first 8-page data is written into the first physical pages p001˜p701 of the physical blocks b00n˜b70n through the 8 channels ch0˜ch7. Then, the chip enable signal line CE1 is activated, and the second 8-page data is written into the first physical pages p011˜p711 of the physical blocks b01n˜b71n through the 8 channels ch0˜ch7. Then, the chip enable signal line CE2 is activated, and the third 8-page data is written into the first physical pages p021˜p721 of the physical blocks b02n˜b72n through the 8 channels ch0˜ch7. Then, the chip enable signal line CE3 is activated, and the fourth 8-page data is written into the first physical pages p031˜p731 of the physical blocks b03n˜b73n through the 8 channels ch0˜ch7. Accordingly, the 32-page data is written into the first superpage sp1 of the n-th superblock sbn. The processes of writing data into the other superpages of the n-th superblock sbn are similar to the above process, and are not redundantly described herein.
For reading data from the superpage, the controlling circuit 110 controls the chip enable signal lines CE0˜CE3 and the channels ch0˜ch7 to read the data from the 32 physical pages. Consequently, the data of the complete superpage can be outputted.
As mentioned above, the controlling circuit 110 of the solid state drive 10 accesses the non-volatile memory 120 according to the superblock configuration. That is, the non-volatile memory 120 comprises plural superblocks, and each superblock comprises plural superpages. Moreover, each superblock is mapped to plural physical blocks, and each superpage is mapped to plural physical pages.
After the opened superblock is full with the write data, the controlling circuit 110 performs a close action and sets the opened superblock as a closed superblock. In addition, the controlling circuit 110 selects another blank superblock of the non-volatile memory 120 as the opened superblock and writes the data into the opened superblock.
When the data in all superpages of the superblock are invalid data, the superblock is erased as a blank superblock by the controlling circuit 110.